DK-DEV-5SGXEA7N【PDF 216/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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SV51008

2014.01.10

Output Registers

7-25

The resynchronization registers are also clocked by the same 0° system clock, except in the DDR3 SDRAM

interface. In DDR3 SDRAM interfaces, the leveling registers are clocked by the write-leveling clock.

The output-enable path has a structure similar to the output path — ensuring that the output-enable path

goes through the same delay and latency as the output path.

Figure 7-14: IOE Output and Output-Enable Path Registers

The following figure shows the registers available in the output and output-enable paths. You can bypass

each register block of the output and output-enable paths.

Data coming from the FPGA core are at half the

frequency of the memory interface clock frequency in

half-rate mode

Used in DDR3 SDRAM interfaces

for write-leveling purposes

Half Data Rate to

Single Data Rate

000

001

010

Alignment Registers

From Core

Output-Enable

Registers

D Q

0

D Q

D Q

D Q

011

100

101

110

111

D Q

0

1

dataout

Double Data Rate

Output-Enable Registers

D Q

From Core

DFF

D Q

1

DFF

DFF

DFF

DFF

enaphasetransferreg

DFF

OE Reg A OE

1

OR2

DFF

<add_output_cycle_delay> enaoutputcycledelay[2..0]

D Q

DFF

0

1

From Core

(wdata2)

Half Data Rate to

Single Data Rate

Output Registers

D Q 0

D Q

D Q

D Q

000

001

010

011

100

101

110

111

Alignment Registers

0

dataout

D Q

OE Reg B OE

Double Data Rate

Output Registers

D Q 0

TRI

DFF

1

DFF

DFF

DFF

DFF

DFF

1

DQ or DQS

From Core

(wdata0)

D Q

DFF

enaphasetransferreg

<add_output_cycle_delay> enaoutputcycledelay[2..0]

000

001

010

011

OE Reg A O

From Core

(wdata3)

D Q

0

D Q

D Q

D Q

100

101

110

111

D Q

0

1

dataout

D Q

DFF

1

DFF

DFF

DFF

DFF

DFF

From Core

(wdata1)

D Q

enaphasetransferreg

OE Reg B O

DFF

<add_output_cycle_delay>

enaoutputcycledelay[2..0]

Half-Rate Clock

From the PLL

Alignment Clock

The write clock can come from either the

PLL or from the write-leveling delay chain.

The DQ write clock and DQS write clock

have a 90° offset between them

Write Clock

From write-leveling delay chains

External Memory Interfaces in Stratix V Devices

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